The present invention relates to a data transmitting/receiving apparatus, and more particularly to a data transmitting/receiving apparatus having a function retransmit data in the event of the occurrence of any transfer error.
A parallel processor system in which a plurality of processing nodes are connected by a network performed retransmission, even where a transfer error occurred within the network during a data transfer between processing nodes, from the processing node on the transmitting side.
This prior art will be described more specifically below.
FIG. 9 is a block diagram illustrating the parallel processor system according to the prior art.
In this parallel processor system, N processor elements 600 (1) to (N), each having a data transferring apparatus 608 provided with a data transmitting apparatus 300 and a data receiving apparatus 400 are connected to one another via an interconnecting network 700.
In FIG. 9, each of the processor elements 600 (1) to (N) has a processor 602, a memory 604, an internal bus 606 and a data transferring apparatus 608 for data communication with other processor elements. Between the data transferring apparatuses 608 of the processor elements 600 (1) to (N) and the interconnecting network 700 are provided external buses 612 (1) to (N), respectively.
Suppose that a transfer error arises within the interconnecting network 700 in this parallel processor system when data are transferred from the processor element 600 (1) to the processor element 600 (N) for instance. Then, on the basis of the actions of the data transmitting apparatus 300 and the data receiving apparatus 400 to be described below, the destination processor element 600 (N) detects a reception error ensuing from this transfer error, and a retransmission request signal is transmitted from the data transferring apparatus 608 in the processor element 600 (N) to the processor element 600 (1). The processor element 600 (1), upon receipt of the retransmission signal, temporarily interrupts its transfer processing, and retransmits the data in which the transfer error arose from the data transferring apparatus 608 in the processor element 600 (1).
FIG. 7 shows a block diagram of the data transmitting apparatus 300 and the data receiving apparatus 400 the data transferring apparatus 608 in a processor element 600 is equipped with. Whereas these apparatuses, provided in the data transferring apparatus 608 of each processor element, transmit and receive data, the description with reference to FIG. 7 supposes that the data transmitting apparatus 300 and the data receiving apparatus 400 are provided in separate processor elements, and data transfers are performed between them.
The data transmitting apparatus 300 is provided with a FIFO memory 302, a FIFO control circuit 304, an ECC circuit 306, a data latch 308, a data selector 310 and a data transmission control circuit 312. And the data transmitting apparatus 300 successively transmits data 16 and, any error is detected of the transmitted data in the data receiving apparatus 400, receives a retransmission request signal 18 returned from the data receiving apparatus 400.
On the other hand, the data receiving apparatus 400 is provided with a data receiving circuit 402 equipped with a data latch 404 and an ECC circuit 406, a FIFO memory 408, a FIFO control circuit 410 and a data reception control circuit 412. Of these, the data latch 404 is a circuit for receiving the data 16 from the data transmitting apparatus 300.
When performing data transmission, the data transmission control circuit 312 in the data transmitting apparatus 300 gives an instruction to the FIFO control circuit 304 to have a datum taken out of the FIFO memory 302. And it causes the data selector 310 to select the datum that has been taken out and to transmit them as the data 16, and causes the data latch 308 to hold that datum. The data transmission control circuit 312 in this manner causes a certain datum (datum n+1) and, having this datum held by the data latch 308, causes the FIFO control circuit 304 to take out the succeeding datum (datum n+2) from the FIFO memory 302 and the data selector 310 to transmit it. After that, it judges the presence or absence of a retransmission request signal for the earlier transmitted datum n+1.
If it finds, as a result of judgment, that no retransmission request signal 18 for the datum n+1 has been received, it has the datum n+2 held by the data latch 308, and updates the datum n+1 held within the data latch until then. And it causes the FIFO pointer of the FIFO control circuit 304 to be updated. After that, it causes the FIFO control circuit 304 to take out the succeeding datum (datum n+3) from the FIFO memory 302 and the data selector 310 to transmit this datum n+3, thereby executing a series of consecutive data transmitting actions.
On the other hand, if it finds, as a result of judgment, that a retransmission request signal 18 for the datum n+1 has been received, it causes the data latch 308 to keep the datum n+1 instead of holding the data n+2, and forbids the FIFO control circuit 304 from updating the FIFO pointer. And it executes the retransmitting action of causing the data n+1, held by the data latch 308, to be transmitted to the data selector 310 as the retransmit datum.
When receiving data, the data reception control circuit 412 in the data receiving apparatus 400 causes the data receiving circuit 402 to receive data sent from the data transmitting apparatus 300. And it causes the data outputted from the data receiving circuit 402 to be stored into the FIFO memory 408.
The data reception control circuit 412, after having a certain datum (datum n+1) stored into the FIFO memory 408 in this manner, causes the next datum sent from the data transmitting apparatus 300 to be received by the data latch 404. After that, it judges the generation or non-generation of an error detection signal 17 for the datum n+1 by the ECC circuit 406. In this process, the FIFO pointer of the FIFO control circuit indicates the area into which the datum n+1 was stored out of all the areas of the FIFO memory 408.
If it is found, as a result of judgment, that no error detection signal 17 for the datum n+1 has been generated, the FIFO pointer of the FIFO control circuit 410 is updated. And the ECC circuit 406 is caused to execute checking and outputting of the datum n+2, and the datum n+2 outputted from the ECC circuit 406 is stored into the FIFO memory 408. After that, a series of consecutive data receiving actions to have the next datum (datum n+3) transferred from the data transmitting apparatus 300 received by the data latch 404 are executed.
On the other hand, if it is found, as a result of judgment, that an error detection signal 17 for the datum n+1 has been generated, a retransmission request signal 18 is transmitted to the data transmitting apparatus 300. At the same time, the pointer of the FIFO control circuit 410 is forbidden from being updated so as to have the datum n+1 stored in the FIFO memory 408 discarded, and checking and outputting of the already received datum n+2 by the ECC circuit 406 are also forbidden so as to discard it. And the retransmit datum, sent from the data transmitting apparatus 300, is caused to undergo execution of reception, checking and outputting by the data receiving circuit 402. After that, a re-receiving action to store the retransmit datum, outputted from the data receiving circuit 402, into the FIFO memory 408 on the basis of the FIFO pointer, which is locked as stated above, is executed.
FIG. 8 is a time chart showing the actions of the data transmitting apparatus 300 and the data receiving apparatus 400 as described above.
In the data transmitting apparatus 300, after transmitting the datum n+1 for instance, the next datum n+2 is consecutively transmitted in a pipeline system without checking the reception or non-reception of a retransmission request signal for the datum n+1. On the other hand, the data receiving apparatus 400, after receiving the datum n+1, consecutively receives the datum n+2 in a pipeline system without checking the presence or absence of any error in the datum n+1. And, if a transfer error occurs for the datum n+1, the data receiving apparatus 400 transmits a retransmission request signal 18 to the data transmitting apparatus 300, and both the received datum n+1 and datum n+2 are discarded within the data receiving apparatus 400. After that, the retransmit datum (R datum n+1) is immediately transmitted from the data latch 308 of the data transmitting apparatus 300 through the data selector 310. Moreover, the next data n+2 is also immediately retransmitted following the R datum n+1.
Incidentally, as what pertains to the prior art described above, what is described in the Gazette of the Patent Laid-open No. Hei 5-61798 is known.
According to the prior art described above, the consecutive transmission of data by the data transferring apparatus 608 is merely consecutive transmission of the datum n+1 through the datum n+3. Furthermore, the transmitting apparatus is provided with a data latch for temporary storage of a datum to be retransmitted separately from the memory, and retransmission is performed only on a datum-by-datum basis. Such a configuration restricts the distance of transfer and the speed of transfer on account of the latching for temporary storage and other reasons.
Furthermore, even if the point where an error has arisen during the processing of a data transfer between processor elements is within the interconnecting network, retransmission should in any case be carried out from the transmitting processor element. Also, if this retransmission is to executed by software in the transmitting processor, the overhead in the system will expand.
Therefore, an object of the present invention is to provide a parallel processor system and a data transmitting/receiving apparatus which makes possible data retransmission from any desired point in the system and is capable of retransmitting a variable number of data and of data retransmission with no restriction on the distance of transfer or the speed of transfer.
In order to achieve the object stated above, in a parallel processing system according to the invention, each of a plurality of processing nodes coupled to one another by at least one switching apparatus transmits data to via the switching apparatus and receives data transmitted from the switching apparatus. Also, the switching apparatus receives transfer data transmitted from one of the processing nodes or another switching apparatus, and transmits the transfer data to the destination processing node or the other switching apparatus. And if any error is detected in the data received by the processing node or the switching apparatus on the receiving side, a request for retransmission of the transfer data is given to the processing node or the switching circuit on the transmitting side, and the processing node or the switching circuit on the transmitting side retransmits the transfer data in response to the retransmission request.
Further in the parallel processor system according to the invention, each of the processing nodes and switching apparatus(es) is provided with a data transmitting/receiving apparatus, and each of the data transmitting/receiving apparatuses is provided with a transfer data buffer for temporarily holding a plurality of data to be transmitted or received, a transmission/reception control means for controlling the transmission/reception of data and the reading of transmit data from and the writing of receive data into the transfer data buffer, an error detecting means for detecting the presence or absence of any error in receive data, and a retransmission control means for issuing, when said error detecting means has detected any error, a retransmission request to the processing node or switching circuit on the transmitting side, and instructing, when it has received a retransmission request issued from the processing node or switching apparatus on the receiving side, said transmission/reception control means to retransmit the data. And the transmission/reception control means, in response to the instruction to retransmit, reads again retransmits the already transmitted data held by the transfer data buffer.
Further, the transfer data buffer is provided with a plurality of data holding areas, and holds data to be transmitted or received in the data holding areas consecutive in the sequence of transmission or in the sequence of reception; and the transmission/reception control means is provided with a buffer control means for controlling a pointer for indicating each data holding area in the transfer data buffer. And the buffer control means, in response to the instruction to retransmit, subtracts a predetermined subtrahend from the pointer at that point of time, successively reads a plurality of already transmitted data equivalent to the subtrahend, held in areas following the data holding area indicated by the subtracted pointer, and the transmission/reception control means successively retransmits the already transmitted data that are read.
As configuration in this manner makes possible processing of retransmission from the processing node or switching circuit on the transmitting side even if a transfer error occurs during a data transfer between a processing node and a switching apparatus, there is no need for the processing node on the transmitting side to perform retransmission processing on every occasion, and the overhead on the retransmission processing by processing nodes can be substantially reduced.
Furthermore, because the number of data to be retransmitted can be made variable, data retransmission can be carried out with no restriction on the speed of transfer and the distance of transfer between apparatuses.